Data placement in NVM hybrid scratchpad-cache hierarchies
Traditional mamory technologies are facing significant limitations as the acaling process advances. The SRAM technology, typically used in different levels of on-chip cache hierarchies, is starting to show integration problems and a high static power consumption due to leakage currents. In the last...
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| Tipo de recurso: | tesis doctoral |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Universidad Complutense de Madrid (UCM) |
| Repositorio: | Docta Complutense |
| Idioma: | inglés |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/107422 |
| Acceso en línea: | https://hdl.handle.net/20.500.14352/107422 |
| Access Level: | acceso abierto |
| Palabra clave: | 004.25(043,2) Memorias (Ordenadores) Computer storage devices Informática (Informática) 1203.17 Informática |
| Sumario: | Traditional mamory technologies are facing significant limitations as the acaling process advances. The SRAM technology, typically used in different levels of on-chip cache hierarchies, is starting to show integration problems and a high static power consumption due to leakage currents. In the last years, several non-volatile memory technologies have been developed (PCM, ReRAM, STT-MRAM, SOT-MRAM, etc.) which solve some of the issues of traditional technologies but with important trade-offs, especially in latency and write energy. In this research thesis, the candidate has explored different solutions to create an efficient memory system architecture. The problem has been approached by mixing different elements and creating heterogeneous memory organizatiosn, both from a technology point of view (SRAM and STT-MRAM) and from a system point of view (hardware controlled cache and software controlled scratchpad)... |
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